NXP Semiconductors /MIMXRT1021 /AIPSTZ1 /OPACR2

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Interpret as OPACR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TP0)OPAC230 (TP0)OPAC220 (TP0)OPAC210 (TP0)OPAC200 (TP0)OPAC190 (TP0)OPAC180 (TP0)OPAC170 (TP0)OPAC16

OPAC18=TP0, OPAC19=TP0, OPAC21=TP0, OPAC20=TP0, OPAC22=TP0, OPAC17=TP0, OPAC23=TP0, OPAC16=TP0

Description

Off-Platform Peripheral Access Control Registers

Fields

OPAC23

Off-platform Peripheral Access Control 23

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC22

Off-platform Peripheral Access Control 22

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC21

Off-platform Peripheral Access Control 21

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC20

Off-platform Peripheral Access Control 20

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC19

Off-platform Peripheral Access Control 19

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC18

Off-platform Peripheral Access Control 18

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC17

Off-platform Peripheral Access Control 17

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

OPAC16

Off-platform Peripheral Access Control 16

0 (TP0): Accesses from an untrusted master are allowed.

1 (TP1): Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus.

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